DK-DEV-5SGXEA7N【PDF 97/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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SV51005

2014.01.10

locked

4-27

You must assert the areset signal every time the PLL loses lock to guarantee the correct phase relationship

between the PLL input and output clocks. You can set up the PLL to automatically reset (self-reset) after a

loss-of-lock condition using the Quartus II MegaWizard Plug-In Manager.

You must include the areset signal if either of the following conditions is true:

? PLL reconfiguration or clock switchover is enabled in the design

? Phase relationships between the PLL input and output clocks must be maintained after a loss-of-lock

condition

Note: If the input clock to the PLL is not toggling or is unstable after power up, assert the areset signal

after the input clock is stable and within specifications.

locked

The locked signal output of the PLL indicates the following conditions:

? The PLL has locked onto the reference clock.

? The PLL clock outputs are operating at the desired phase and frequency set in the MegaWizard Plug-In

Manager.

The lock detection circuit provides a signal to the core logic. The signal indicates when the feedback clock

has locked onto the reference clock both in phase and frequency.

Clock Feedback Modes

This section describes the following clock feedback modes:

?

?

?

?

?

?

Source synchronous

LVDS compensation

Direct

Normal compensation

ZDB

EFB

Each mode allows clock multiplication and division, phase shifting, and programmable duty cycle.

The input and output delays are fully compensated by a PLL only when using the dedicated clock input pins

associated with a given PLL as the clock source.

The input and output delays may not be fully compensated in the Quartus II software for the following

conditions:

? When a GCLK or RCLK network drives the PLL

? When the PLL is driven by a dedicated clock pin that is not associated with the PLL

For example, when you configure a PLL in ZDB mode, the PLL input is driven by an associated dedicated

clock input pin. In this configuration, a fully compensated clock path results in zero delay between the clock

input and one of the clock outputs from the PLL. However, if the PLL input is fed by a non-dedicated input

(using the GCLK network), the output clock may not be perfectly aligned with the input clock.

Clock Networks and PLLs in Stratix V Devices

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